Recently, developments of semiconductor apparatuses that incorporate semiconductor devices exhibiting different functions into one chip and realize higher functions using a dielectric separation technique have been explored vigorously. In particular, apparatuses that incorporate power semiconductor devices therein have been realized by combining various process techniques, such as a trench formation technique, an oxide film burying technique, a silicon epitaxial growth technique, and a surface smoothing techniques including a chemical mechanical polishing (CMP) technique. The apparatuses formed by the combination of these techniques include a switching power supply that incorporates a control IC and power semiconductor devices into a unit, a Bi-CMOS apparatus formed by combining the trench separation techniques, and an apparatus, comprised of a MOSFET and a thyristor, that exhibits composite functions.
In the field of power supply IC, a switching power supply that uses one chip IC, into which power semiconductor devices exhibiting a high breakdown voltage and a control IC are incorporated, has been used widely by virtue of its small size and light weight. The switching power supply has been employed in portable equipments including a mobile telephone and a camera for the mobile telephone, a power supply for lights, a power supply for driving a motor, and such equipments. The maximum commercial AC power supply voltage is as high as 240 V (effective value) worldwide. In this case, the peak voltage can be as high as 680 V. Therefore, it is necessary for the semiconductor apparatuses to exhibit a breakdown voltage of around 700 V as the rated voltage thereof.
Among the component parts for the switching power supply, a capacitor and a transformer occupy large areas. It is possible to reduce the sizes of the capacitor and transformer by increasing the frequency of the switching power supply. Therefore, a frequency in the range between 100 kHz and 200 kHz is used widely. For the power semiconductor device, the MOSFET exhibiting low switching losses and excellent process compatibility with the control IC is employed. Since the MOSFET is a majority carrier device that does not cause any conductivity modulation based on the minority carrier injection, the MOSFET exhibits a high ON-resistance.
The ON-resistance reduction techniques innovated recently, however, allow the MOSFET to reduce its ON-resistance. The ON-resistance reduction techniques include changing the conventional planar gate structure to a three-dimensional gate structure including trenches formed perpendicular to the semiconductor substrate surface to shorten the unit cell pitch and to increase the channel density. The ON-resistance reduction techniques also include forming a multilevel reduced-surface-electric-field structure (hereinafter referred to as “RESURF structure”). But the ON-resistance reduction techniques described above complicate the MOSFET structure and its manufacturing process. As a result, the throughput of non-defective products and the manufacturing costs are affected adversely.
The IGBT exhibits a self-arc-extinguishing function in the same manner as a MOSFET and a low ON-resistance in the same manner as a bipolar transistor. By virtue of the merits thereof, IGBTs are employed widely especially for high voltage and high current use. Although the IGBT ON-resistance is reduced by enhancing the conductivity modulation effects by injecting minority carriers from the anode region to the base region, the turn-off loss increases. In other words, a tradeoff relation exists between the ON-resistance and the turn-off loss. The carriers that diffuse out of the current path and do not contribute to the conductivity modulation increase the turn-off loss.
Recently, an IGBT that includes a silicon on insulator (SOI) structure has been used in practice. The SOI structure confines the carriers within a thin n-type silicon active layer by dielectric separation to reduce the switching losses of the IGBT. See published Japanese Patent Application Hei. 6 (1994)-318714, where, although the n-type silicon active layer and a buried oxide film (hereinafter referred to as a “BOX layer”) divide the voltage, the BOX layer as thick as 1 to several μm is used to obtain a high breakdown voltage, since the n-type silicon active layer is 1 μm or thinner.
FIG. 13 schematically illustrates a cross-sectional view of the conventional SOI semiconductor device described in the above publication. As shown in FIG. 13, the SOI semiconductor device includes a voltage dividing structure, a first potential distribution improving structure, and a second potential distribution improving structure for obtaining a high breakdown voltage. The voltage dividing structure includes a thick BOX layer 52, several μm in thickness, formed on a semiconductor substrate 51 and beneath a p-type anode region 55, that divides the breakdown voltage. The first potential distribution improving structure reduces the edge curvature beneath an n-type cathode region 54 by changing the impurity concentration in multiple steps to prevent breakdown from occurring in the edge portion beneath the n-type cathode region 54. The second potential distribution improving structure uses a very resistive thin film 53 including one end connected to an anode electrode 57 formed on the p-type anode region 55 and the opposite end connected to a cathode electrode 56 formed on the n-type cathode region 54. The thick BOX layer 52 described above is usually expensive since it is formed by joining together silicon wafers, each having an oxide film thereon, and polishing one of the wafers. The very resistive polysilicon thin film 53 formed in the surface has reliability problems in the high temperature and high humidity environments.
Japanese Patent Application Hei. 7 (1995)-122750 discloses a structure that reduces the capacitance between the drain and source of a vertical MOSFET employing the separation by an implanted oxygen (hereinafter referred to as the “SIMOX”) technique that facilitates forming a buried oxide film locally in an arbitrary region by implanting oxygen ions. The structure here does not necessarily focus its target of a structure for sustaining the breakdown voltage of lateral semiconductor devices.
Japanese Patent Application Hei. 8 (1996)-64687 discloses a semiconductor apparatus that facilitates high-speed operations without affecting the provision of a higher breakdown voltage by electrically connecting lateral MOSFETs spaced apart from each other by a SOI structure. The lateral MOSFETs are connected electrically to each other with a very resistive region disposed below a buried oxide film formed below the MOSFETs.
Japanese Patent Application 2003-303828 discloses a technique for forming a buried oxide film below the emitter region of a lateral bipolar transistor for realizing a high amplification factor and low base resistance simultaneously in the lateral bipolar transistor.
Japanese Patent Application 2000-357665 discloses a SIMOX method that facilitates forming a thin buried oxide film locally. Recently, the techniques for forming a thin buried oxide film by the SIMOX method have been advanced remarkably.
A SOI structure is obtained by the aforementioned SIMOX method that forms a thin buried oxide film by combining oxygen ion implantation and subsequent annealing. Therefore, SOI semiconductor devices have been obtained with low manufacturing costs. Nonetheless, since the buried oxide film formed by the SIMOX method is very thin, several hundreds nm or thinner, it is difficult to obtain a high breakdown voltage. Therefore, the SIMOX method is evaluated to be a method for forming a SOI oxide film suited mainly for obtaining a logic circuit IC exhibiting a low breakdown voltage.
In view of the foregoing, there remains a need for a SOI lateral semiconductor device that facilitates a high breakdown voltage while sustaining low switching losses even when the SOI lateral semiconductor device includes a thin buried oxide film formed therein by a SIMOX method. The present invention addresses this need.